Random Access Memory chip
DDR, DDR2 and DDR3 are different versions of Random Access Memory (RAM). This is the type of memory that stores the information the processor requires to execute the operations called for by the applications currently in use. All versions of DDR are based on SDRAM, which synchronizes the storage and transfer of data to the computer's clock cycle. To better understand the DDR family of memory, it's important to understand both clock cycle and prefetch buffers, two key elements of RAM operation.
Clock Cycle
All computers have an internal clock in the form of a chip containing a crystal that vibrates at a consistent frequency when applied to electricity. This frequency is knows as the clock rate. Each vibration of the crystal represents one clock cycle. The clock cycle is the shortest amount of time in which the computer can execute an operation. The reliability of the clock rate allows for the synchronization of computer activities, including those of RAM and the computer's Central Processing Unit (CPU).
Prefetch Buffer
RAM is, essentially, a bunch of electrical switches or "transistors." Each transistor is attached to a capacitor, which is capable of storing charge. A closed transistor blocks current, leaving its capacitor empty, thus representing a "0." An open transistor allows current to flow through, charging its capacitor so it represents a "1." The transistors are situated into rows and columns. In older versions of RAM, the computer would have to send a different request each time it accessed data on a given row. A prefetch buffer reads not only the data requested, but also data adjacent to it on its row, thus providing the processor with more of the "datawords" it needs per memory access.
DDR
DDR stands for Double Data Rate. Like SDRAM, it operates at the rate of the computer's clock cycle. However, unlike SDRAM, it can transfer data twice per clock cycle. It does this by using the rising and falling edges of the clock signal, also known as "double pumping" and employing a prefetch buffer capable of accessing two datawords at a time. This means that it can store and move a value in the same amount of time it takes SDRAM to do one or the other, effectively doubling the memory's speed.
DDR2
DDR2 also utilizes the same double pumping technique as DDR. It achieves performance gains by using a prefetch buffer that retrieves four datawords per memory access. This allows it to transfer data four times per clock cycle (compared to twice in the case of DDR). According to Bit-Tech.com, its improved efficiency allows it to consume less power than DDR.
DDR3
Like all other forms of DDR, DDR3 transfers data twice per clock cycle. However, its prefetch buffer can access eight datawords at a time, according to Benchmark Reviews. Thus, it can transfer data eight times per clock cycle, giving it a maximum data transfer rate twice that of DDR2 while using less power.
Tags: clock cycle, prefetch buffer, transfer data, Access Memory, amount time, clock cycle